Degradation of the high-k dielectric/metal gate stacks under electrical stress

Recent HK reliability studies reflect increasingly complex and diverse gate stack structures fabricated to meet device scaling requirements. Essential progress towards achieving low values of the threshold voltage was made through the introduction of the metal oxide capping layers in gate stacks that, in turn, instigated a number of reliability studies of these systems. Employing fast measurements techniques has provided new insights into the characteristics of the defects in the gate stacks. Interfaces between the high-k dielectrics and high mobility substrates (III-V and Ge), which are being considered for use in transistors in the future technology nodes, have started to attract significant interest from reliability standpoint. In the present study, we focus on the breakdown mechanism of the scaled high-k/metal transistor gate stacks targeting high performance logic applications.